Periodic signals are used in a variety of applications and devices. Clock signals are a type of periodic signal used to establish signal timings for various operations and commands. For example, in some memory devices, such as synchronous dynamic random access memory (SDRAM), data signals may be read and written synchronized relative to various clock signals. For example, read data is typically retrieved from the memory device based on a read data strobe signal. Write data may be latched in a memory device based on a write data strobe signal. The signals for read, write, and other operations, and their relationship between each other, are typically synchronized to, and based on, internal and/or external clock signals.
For example, one type of conventional quadra-phase design utilizes a phase locked loop (PLL) with multiple adjustable delay lines or analog cells. These conventional designs, however, require long initialization times, spanning multiple clock cycles, and require high power consumption. Moreover, many conventional designs employ a clock divider. When using a divided clock, if the phase of each multi-phase output signal has a 90-degree offset in phase from the previous phase (for example, 0-degrees, 90-degrees, 180-degrees, and 270-degrees), each multi-phase output clock signal has half of the input clock frequency, and each multi-phase output clock signal has a period that is twice that of the original input clock period.